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"The best class I have ever taken! The lecture was thorough. The labs were fun and critical to understanding the concepts."

Workshop Descriptions

Click here to download the full syllabus for all Sutherland HDL workshops (a PDF document).

Sutherland HDL offers three types of expert-level training workshops:

On-site Workshops

Sutherland HDL on-site training workshops are held at your facilities and presented by expert instructors. Training can be scheduled at a time and location that is most effective for an engineering team. Course topics can be customized to meet the needs of the engineering team. All that is required is a conference room. Sutherland HDL can provide a portable lab environment, with computers, simulation and synthesis software.

eTutored™ live Online Workshops

Sutherland HDL eTutored™ live online workshops are instructor-led workshops that provide all the same learning benefits as classroom based training, but with greater flexibility to mix expert training and work responsibilities.

Details

eTutored™ self-paced Online Workshops (available Q3-2011)

Instructor-assisted comprehensive training anytime and anywhere — the utmost in schedule flexibility. Sutherland HDL eTutored™ self-paced online courses provide one-on-one tutoring from experienced SystemVerilog experts.

Details

SystemVerilog for Design and Synthesis

4 or 5 day comprehensive training on the latest generation of the SystemVerilog language
Emphasizes the synthesizable subset of Verilog and SystemVerilog
Audience: This workshop is for digital engineers who will be designing ASICs, FPGAs or systems with Verilog.

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SystemVerilog Verification Foundations

4 to 5 day advanced-level workshop on using SystemVerilog for verification
Presents the concepts of object-oriented verification
Discusses classes, semaphores, mailboxes, dynamic arrays, constrained random testing, and coverage
Emphasizes creating advanced-level testbenches and verification programs
Audience: This workshop is for design and verification engineers who will be verifying digital designs

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eTutored™ Workshop Schedule
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Mastering UVM (Universal Verification Methodology)

3 or 4 day workshop on developing testbenches using the UVM verification standard
Emphasis on proper verification methodology
Audience: This workshop is for verification engineers who are already familiar with the SystemVerilog verification constructs

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eTutored™ Workshop Schedule
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Advanced SystemVerilog Assertions for Design and Verification Engineers

2-day advanced-level workshop writing SystemVerilog Assertions
Students learn to write complex assertion sequences for a variety of complex digital logic circuits
Audience: Both design engineers and verification engineers will find this course beneficial

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eTutored™ Workshop Schedule
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